One of the well-known electrically programable/erasable non-volatile memory devices is non-volatile memory transistor made of stacked-gate field-effect transistor, wherein programing is conducted by means of hot electron mechanism, and erasing by Fowler-Nordheim tunneling mechanism. In the stacked-gate non-volatile memory transistor, hot electron generated in diffusion layer is implanted in floating-gate electrode to change electric charge of floating-gate electrode. Thus, threshold voltage of transistor is changed, and information recorded. Typical construction of above mentioned stacked-gate non-volatile memory transistors is as shown in FIG. 6 by its cross-sectional view. Referring to FIG. 6, thin silicon oxide layer 2, which is tunneling medium, is formed on P-type silicon substrate 1. On silicon oxide layer 2 is floating-gate electrode 3. In silicon substrate, there are N-type diffusion layers, viz., source 4 and drain 5. On top-of floating-gate electrode 3, control-gate electrode is formed with silicon oxide layer 6 in between.
Recently, however, in order to increase programing speed of stacked-gate non-volatile memory transistor a new memory cell having DSA (Diffusion Self Align) structure as shown in FIG. 7 is proposed. In DSA structure, P-type (being the same conductive type as substrate) impurity layer is formed by means of ion-implantation to drain in self-aligning manner; in this way the impurity density of substrate at drain edge is enhanced to help easier occurrence of electric field concentration, thus the efficiency of hot electron generating is increased. Referring to FIG. 7, 1 indicates P-type silicon substrate, 4source, 5 N-type diffusion layer, or drain region, 8 high density P-type diffusion layer that has been formed to the drain in self-aligning manner, 2 thin silicon oxide layer, or tunneling medium, 3 floating-gate electrode, 6 silicon oxide layer, or insulation layer, and 7 control-gate electrode. FIGS. 8(a)-8(f) shows prior art manufacturing method of DSA structure as shown in FIG. 7. First, as shown in FIG. 8(a), form silicon oxide layer 9 on P-type semiconductor substrate 1 providing openings for regions of source 4 and drain. 5, and then apply photoresist mask 10 to cover source region 4. Next, as-shown in FIG. 8(b), Boron ion-implantation using silicon oxide layer 9 and photoresist mask 10 as masks, to form high density P-type diffusion layer 8 in drain region 5. Then, as shown in FIG. 8(c), remove photoresist mask 10. After that, as shown in FIG. 8(d), high temperature (1000.degree. C. .about.1100.degree. C.) heat treatment to expand region of high density P-type diffusion layer 8 to reach underneath silicon oxide layer 9. Then, as FIG. 8(e) shows, ion-implantation of Arsenic or Phosphorus with silicon oxide layer 9 as masks, to form high density N-type diffusion layers, or source 4 and drain 5. After these, as shown in FIG. 8(f), after removing silicon oxide layer 9, form silicon oxide layer 2 as tunneling medium, floating-gate electrode 3, silicon oxide layer 6, and control-gate electrode 7; DSA structure is thus formed.
Along with the needs for higher integration density in the field of non-volatile memory devices the channel length under floating-gate electrode 3 is requested to be made shorter. Under such situation, prior art manufacturing method of DSA structure which employs diffusion process accompanying high temperature heat treatment faces a difficulty in controlling diffusion depth of high density P-type diffusion layer 8; this makes manufacturing of finer pattern devices very difficult.
This invention is intended to solve above mentioned difficulty, and offers a new manufacturing method for floating-gate semiconductor memory devices having DSA structure; wherein high temperature diffusion process is eliminated, making it easier to manufacture finer pattern devices.